Nanoscale Details of Photolithography Process

Schematic of the photolithography process shows the formation of a gradient extending from the photoresist material to be removed (center) into the unexposed portions of the resist on the sides. NIST measurements document the residual swelling fraction caused by the developer that can contribute to roughness in the final developed image.

Researchers at the National Institute of Standards and Technology (NIST) have made the first direct measurements of the infinitesimal expansion and collapse of thin polymer films used in the manufacture of advanced semiconductor devices. It's a matter of only a couple of nanometers, but it can be enough to affect the performance of next-generation chip manufacturing. The NIST measurements, detailed in a new paper,* offer a new insight into the complex chemistry that enables the mass production of powerful new integrated circuits.

The smallest critical features in memory or processor chips include transistor "gates." In today's most advanced chips, gate length is about 45 nanometers, and the industry is aiming for 32-nanometer gates. To build the nearly one billion transistors in modern microprocessors, manufacturers use photolithography, the high-tech, nanoscale version of printing technology. The semiconductor wafer is coated with a thin film of photoresist, a polymer-based formulation, and exposed with a desired pattern using masks and short wavelength light (193 nm). The light changes the solubility of the exposed portions of the resist, and a developer fluid is used to wash the resist away, leaving the pattern which is used for further processing.

Exactly what happens at the interface between the exposed and unexposed photoresist has become an important issue for the design of 32-nanometer processes. Most of the exposed areas of the photoresist swell slightly and dissolve away when washed with the developer. However this swelling can induce the polymer formulation to separate (like oil and water) and alter the unexposed portions of the resist at the edges of the pattern, roughening the edge. For a 32-nanometer feature, manufacturers want to hold this roughness to at most about two or three nanometers.........